A MCM Design Announcement

MCM Design is pleased to announce a breakthrough in the high resolution RAM configuration for the 1970s Bally Arcade 3 custom chip set. Up to now, four 4KB banks of dynamic RAM were required to operate the 2 Bally custom address and data chips in the high resolution mode. Since each bank utilizes 8 DRAM chips, a total of 32 DRAM chips was necessary. However, MCM Design has developed, built and tested a prototype wire wrapped RAM board which can operate the same 2 custom chips in high resolution using only 4 static RAM chips. MCM Design's breakthrough static RAM configuration also offers single +5VDC power supply operation with optional user programmable multipage screen RAM capability.

Below is a listing showing the major chip differences between MCM Design's new hi-res static RAM scheme and the coin op arcade Seawolf II.

                                                	MCM Design			Seawolf II
				scheme			scheme

RAM				4 static RAM chips		32 DRAM chips
				4KB x 8 bit			4KB x 1 bit
				4KB capacity minimum		4KB capacity minimum
				120 nsec access time
				(or faster)

video data bus			four 74LS245			one 74LS245 (optional)
				bidirectional receiver		four 74LS253 (read only)

data bus enable		74LS138
				enable selector
				74LS132
				selector decoder

active-low RAS clock		74LS123
                                                                2 inverter gates

row address latch in		74LS373

active-low			74LS175
CAS0, CAS1, CAS2, CAS3
generation
				_______			______

Total chips			     13				    37

 The total chip count for MCM's new scheme is 25 chips. A few more chips must be added to:

1. Run the screen RAM in low or hi-res modes.
2. Multipage the screen RAM.

HOW THE NEW SCHEME WORKS

The new RAM timing scheme is a variation of the scheme used by the DATAMAX UV-1R computer. Three DATAMAX UV-1R schematics are archived on the Bally Alley website in the Documentation/ High-Res Astrocade Upgrade/ High-Res Package 3 section.

Memory Address Selection

The active-low row address strobe RAS is generated from the negated system clock ɸ (phi) using a 74LS123 chip and 2 inverter gates. The memory row address, from the custom address chip lines MA0-MA5, appears first and is fed to a 74LS373 latch. This row address is latched at the static RAM chip A0-A5 input pins by the active-low RAS line.

The memory column address on the same MA0-MA5 lines appears next and is also wired to the static RAM chip A6-A10 input pins.

Both the row and column addresses now present at the static RAM address pins are then latched into the static RAM chip by the active-low CAS line which acts as the RAM chip's enable (select) line.

Bank Select

The four custom address chip lines RAS0, RAS1, RAS2 and RAS3, which are used as the RAM bank select, are fed thru two 74LS175 quad D-type flip-flops to generate the four static RAM chip  active-low enable lines CAS0, CAS1, CAS2 and CAS3.

The 8 Bit Data Bus

A static RAM chip shares its 8 bit data in/out lines. The two DATEN and active-low Write Enable (WE) lines determine if data on the 8 bit data bus MD0-MD7 is to be written (input) into the RAM chip or read (output) from the RAM chip.

The  8 bit data bus from each RAM chip is wired to one of four specific 74LS245 bidirectional receivers. The line side of each of these 4 chips are all wired to the custom data chip MD0-MD7 pins. The custom data chip DATEN line is wired to the Direction (DIR) pin of each 74LS245 to direct the data flow as a write or read. A decoded enable line is also wired to each 74LS245 enable input so that only the appropriate 74LS245 will be enabled (turned on) at the right time to avoid any data conflicts.

Screen Refresh (Scan)

When all 4 RAS0, RAS1, RAS2 and RAS3 lines are simultaneously active-high, a TV display refresh (scan) is generated. All four 74LS245 receivers are disabled at this time. This scan acts like a memory read. One byte from all 4 RAM banks is read simultaneously. So, these 4 bytes (32 bits) of data are fed to the four 74LS166  chip shift data inputs. An active-low Shift Load (S/L) input to the four chips indicates when the data is valid and ready to be shifted serially, two bits at a time by the 7M clock, into the custom data chip using the two Serial 0 and Serial 1 lines. Apparently, there is a 12 bit address counter in the custom data chip which keeps track of the row and column addresses, so the entire screen RAM is scanned. So, 4 bytes (16 pixels) at a time are shifted into the custom data chip every time the S/L line goes low.

MCM DESIGN's  INTENT WITH THIS NEW HI-RES SCHEME

This new static RAM scheme was developed for personal use with the Bally/Astrocade home computer system to supersede MCM Design's original hi-res Astrocade and to utilize this second modified Astrocade as a purely hi-res gamer. In order to implement the new static RAM scheme, modifications MUST be made to the Astrocade's motherboard. The primary modifications are listed below.

1. Remove the 8 DRAM chips and also chip U23.
2. Remove from ground, the Serial 0 and Serial 1 input lines at the custom data chip.
3. Move the 27 ohm, 1W power resistor R1 over about 1 inch, so a 28 pin ribbon cable WW socket can be     mounted on the motherboard.
4. Tap 28 specific motherboard lines to the WW socket using #30 wrapping wire, one end soldered to the motherboard, the other end wrapped to the WW socket.

No connection to the Astrocade motherboard 50 pin expansion is necessary to operate this new hi-res static RAM scheme.

MCM Design is announcing this new scheme and plans to post detailed scheme documentation on the Bally Alley website for a high tech minded individual desiring to take the challenge and build a "modified for hi-res Astrocade" which can run in the low or high resolution modes. MCM Design also plans to convert certain low-res Astrocade games into hi-res. Note that over 8KB conversions will need to run on 32KB user RAM addressed 8000-FFFFH. Some hi-res demos are already included in the 8KB BalcheckHR package already archived on the Bally Alley website.

MCM Design is extremely pleased with the results of this new hi-res static RAM prototype board. It runs perfect in low and hi-res and has a low chip count. It is awesome! MCM Design will now develop  and test the option for multi-paging the screen RAM. 

I would like to thank Ken Lill for his recommendation to me in purchasing the 16 channel Kingst logic analyzer, which resolved several project problems. I would also like to thank Anthony Miller for his detailed "A Description Of The Bally Professional Arcade Video Hardware And Associated Coin-Operated Hardware" and the Bally Alley for posting the documentation. This doc detailed the hi-res screen refresh (scan) function and circuitry, which was a major help in understanding and resolving this project's final problem. Without this outside help, I would have never successfully completed my hi-res static RAM project scheme. Thanks for your help.

MCM Design
Sept 2018